`timescale 1ns/1ns
module iic_test;
reg CLK_50M;
reg RSTn;
wire [3:0] LED;
wire SCL;
reg SDA;
wire SDA;
eeprom_test
U2(
 input CLK_50M,
input RSTn,
output [3:0] LED,
output SCL,
inout SDA
);
  initial
  begin
    CLK_50M=0;
    
    #1000 rst_n=1;
    #500 key_wr=0;
    #3000 key_wr=1;
    #4000 key_rd=0;
    #300 key_rd=1;
end
always #10 CLK_50M=~CLK_50M;
endmodule